The present invention relates to a dynamic type semiconductor memory device, and more particularly to a dynamic memory employing a shared sense amplifier scheme.
Memory capacity of dynamic memories has been increasing remarkably and 1 Mega-bit dynamic memories are becoming popular in the field. Accompanied by the increase in the memory capacity the number of memory cells connected to each bit line is also increased, and therefore the effective capacitance of the bit line is increased. Since a level of a signal read out to a bit line from a selected memory cell is determined by a ratio of a capacitance CM of a memory cell to the bit line capacitance CD, i.e. CM/CD the increase in the number of memory cells to the respective bit lines lowers the read out signal on the bit line, and it was difficult to sense a read out signal on a bit line with a high sensitivity and at a high speed.
In order to solve the above disadvantage, the so-called shared-sense amplifier scheme has been proposed and advantageously employed in 256K-bit and 1 Mega-bit dynamic memories. According to the shared-sense amplifier scheme, memory cells associated with each sense amplifier are arranged two or more pairs of bit lines and only one pair of bit lines are selectively connected to the sense amplifier. Accordingly, the manner of memory cells connected to each bit line is reduced and therefore the effective capacitance of the bit line is effectively reduced to increase the sensitivity in reading a signal from a selected memory cell. The details of the above shared-sense amplifier scheme is disclosed in the U.S. Pat. No. 4,366,559 issued to Misaizu et al.
In dynamic memories, a plurality pairs of bit lines are arranged in parallel with each other. Half the bit lines are arranged in parallel at one side of the sense amplifiers and another half the bit lines are arranged in parallel at the other side of the sense amplifiers, in the typical shared-sense amplifier scheme. In a read operation, the bit lines at one or another side of the sense amplifiers are electrically connected to the sense amplifiers and subjected to amplification by the sense amplifiers. Through the amplification, in the above one side bit lines, each pair of bit lines which have been precharged to a predetermined level, are changed to different potentials. Particularly, one of each pair of bit lines is discharged to the ground potential. Since the bit lines are arranged in parallel, a stray capacitance C.sub.BB present between each adjacent two bit lines. Therefore, a change in potential at one bit line affects its adjacent bit line or lines as noise through the stray capacitance C.sub.BB.
This reduces an operational margin in the memories and substantially lowers the sensitivity in reading.